Semiconductor research giant Imec has unveiled its latest process technology roadmap, offering a rare glimpse into how chipmakers plan to navigate the next two decades of innovation. The updated roadmap, developed in collaboration with industry leaders like TSMC, Intel, and Samsung, outlines a gradual transition toward ultra-small fabrication nodes while addressing the growing complexity of transistor scaling.
Beyond Traditional Scaling: The Shift to Angstrom Nodes
Imec’s projections indicate that the industry will reach 0.3nm (3 angstrom) fabrication technologies by 2038, a milestone that would redefine Moore’s Law by prioritizing cell density over raw node scaling. However, the roadmap also signals a potential slowdown in contact poly pitch (CPP) reduction, with scaling expected to plateau at the A10 generation around 2030. This shift reflects the increasing difficulty of shrinking transistors while maintaining performance and power efficiency.
Chipmakers are now adopting a staggered approach to process node introductions, typically rolling out a new node every three years with incremental updates in between. For example, TSMC has already deployed N3B (2023), N3E (2024), and N3P (2025), while Intel’s 18A and 18A-P nodes are slated for 2025 and 2027, respectively. Imec’s roadmap suggests this pattern will continue, with future nodes focusing on enhancing existing architectures rather than introducing entirely new ones.
The N2 Era: Performance and Efficiency at 2nm
According to Imec, the industry is currently transitioning into the 2nm (N2) era, characterized by a CPP of around 48nm, a cell height of 132nm, and a 6-track architecture. Julien Ryckaert, Imec’s vice president of R&D, emphasized that this generation marks a shift toward nanosheet transistors, which enable deeper scaling into the angstrom range. While Intel’s 18A and TSMC’s N3 nodes currently operate at similar CPP levels, Imec’s projections suggest that performance and efficiency enhancements will drive the next wave of node development.
Ryckaert noted, “We are extending our logic roadmap beyond N2, where the nanosheet era will take us deep into the angstrom node. This transition is already underway, and it will fundamentally reshape how we approach transistor design.”
A14 and A10: The Next Milestones in Density
Imec expects the A14-class technology to emerge in 2028, with high-volume manufacturing beginning in 2029. This generation is projected to feature a CPP of 45nm, a cell height of 115nm, and a 5.5-track architecture. The A10-class, slated for 2030–2031, will further reduce CPP to 42nm and cell height to 98nm, though it will still rely on a 5.5-track design. Notably, Imec suggests that gate-all-around (GAA) transistors may be implemented with either frontside or backside power delivery networks, depending on application needs.
High-NA EUV lithography tools are expected to play a role at the A14 generation, aligning with Intel’s plans but diverging from TSMC’s current strategy. This divergence highlights the industry’s fragmented approach to adopting cutting-edge manufacturing techniques.
CFET Transistors: A Vertical Leap in Scaling
The most significant innovation in Imec’s roadmap is the introduction of CFET (complementary field-effect transistor) technology at the A7 generation, expected around 2033. Unlike traditional nanosheets, CFETs stack n-type and p-type transistors vertically, adding a third dimension to scaling. Imec’s projections position CFETs as the leading candidate for A7, potentially replacing conventional nanosheet architectures that face practical scaling limits.
While the A7 generation will maintain a CPP of 42nm, it will reduce cell height to approximately 80nm and transition to a 4.5-track architecture. Ryckaert explained, “Moving into A7, we see increasing challenges in scaling conventional nanosheet devices. CFETs offer a viable path forward, but their adoption will depend on overcoming integration and manufacturing hurdles.”
The Path Forward: Balancing Innovation and Practicality
Imec’s roadmap underscores the semiconductor industry’s struggle to balance innovation with practicality. While 0.3nm nodes and CFET transistors represent groundbreaking advancements, their adoption will require significant investment in research, development, and infrastructure. The roadmap also highlights the industry’s growing reliance on collaborative efforts, as chipmakers, equipment suppliers, and research organizations work together to push the boundaries of what’s possible.
As the industry approaches the early 2030s, the focus will shift from sheer node scaling to optimizing cell density, power efficiency, and performance. Imec’s predictions serve as a roadmap for the future, but the actual pace of innovation will depend on technological breakthroughs, economic factors, and global supply chain dynamics. For now, the industry remains committed to redefining Moore’s Law—not by abandoning it, but by evolving it to meet the demands of a rapidly changing technological landscape.
AI summary
Imec’in yeni yol haritasıyla yarı iletken üretiminde 0,3 nanometre düzeyine ulaşılması hedefleniyor. CFET transistörleri ve Hyper-NA EUV litografi gibi yenilikler sektörü nasıl değiştirecek?
